duplicate of a original document from amcc S5933QE pci controller device summary
duplicate of a original document from amcc s5933 pci controller device summary S5933QE devices pci S5933QE matchmaker device summary revision 2, november 1, 1997 the following are all known device and document variations for the amcc S5933QE pci matchmaker and 1997 device data book. the workarounds described below are factory suggestions and are not to imply the only or all possible solutions. contact your local field application engineer for new workaround developments. also con tact your fae for the latest design notes and data book corrections or see the amcc home page at www.amcc.com . d8: bus master burst write operation with an asynchronous fifo interface description : when performing a b us master write to the pci bus, if only one location of the fifo remains full, the s5933 deasasserts frame# on the next clock to indicate the last data phase is in progress. if another value is written from the add - on at the right moment, an internal condi tion may cause irdy# to remain asserted to sustain the burst, but frame# has already been dasserted. workaround: externally synchronizing wrfifo# or wr# to bpclk moves the rising edge of the write strobe to prevent this event from occuring. request separa te d8 applications note from your local fae for more detail. status: no factory d8 alteration planned . d14.1: false add - on to pci fifo empty indication description : if the last data in the add - on to pci fifo is written by the s5933 to the pci bus an d receives a target retry, the fwe output and add - on to pci fifo status bits will go active, indicating that the fifo is empty, even though the final data has not yet been transferred. this is only a problem when using add - on initiated bus mastering when f we is used as a condition to deassert amwen at the end of a bus master write. using fwe in this way could cause amwen to be deasserted before the last bus master write has successfully completed. workaround: instead of using fwe, the add - on interrupt signa l, irq#, can beconfigured to go active when the transfer count reaches zero. the transfer count is only updated when data is successfully written. note : when fwe and the status bits indicate that the add - on to pci fifo is empty, there are 8 empty locatio ns in the fifo. the data for the transfer which received the retry is stored in a holding register and is not involved. status: no factory d14.1 alteration planned. d17: pci to add - on fifo loses data when written w/o all pci byte enables asserted de scription: when writing to the fifo from the pci side (as a target), if the byte enable for the specified byte lane is not active, then that data could be lost. the problem is encountered when the s5933 operation registers are mapped to i/o and the fifo is written to 16 bits at a time, alternating between bytes 0,1 and bytes 2,3. under certain conditions internal to the s5933, when the byte enable for the fifo advance byte lane is not active, the data written is not captured by the fifo. workaround 1: alwa ys write the fifo with the byte enable that corresponds to the fifo advance byte lane active. workaround 2: always perform 32 - bit fifo writes from the pci bus. status : no factory d17 alteration planned. (11 - 19 - 97) page 1
duplicate of a original document from amcc s5933 pci controller device summary S5933QE devices b1: pci bus hang when s5933 pci initiated bus mastering is disabled and the s5933 has gnt# description: s5933 pci initiated bus mastering hangs the bus when the s5933 gets gnt# when another master is disabling bus mastering through the mcsr register before the transfer count reaches 0. this only occurs when the pci bus arbiter offers gnt# to the s5933 while another master is executing a transaction on the pci bus. if the active transaction disables s59 33 bus mastering, then the s5933 will start a bus master transaction, then realize its bus mastering is disabled and hang on the bus with frame# active. workaround 1: use the s5933 transfer count register(s) going to 0 in order to get the s5933 to stop bu s mastering before it is disabled through the mcsr. the transfer counts should be programmed for the number of bytes that need to be transferred. when that number of bytes has been transferred, the s5933 will get off the bus normally. workaround 2: write the transfer count to 4. this safely aborts the bus master transfer after one more pci transaction. then bus mastering can be disabled through the mcsr. status : no factory b1 alteration planned. b2: s5933 bus master writes to bus master read address when bus master write has priority over bus master read description: when bus master writes are set up to have priority over bus master reads (mcsr register, bit 12=0, bit 8=1) and both bus master writes and reads are enabled at the same time, then the s5933 could write to the read address. workaround: set the bus master write and read to the same priority. status : no factory b2 alteration planned. 1997 data book timing call out error description: chapter 13, page 13 - 11 shows time t 165 for rdempt y valid as 15 ns maximum. this should be 12 ns maximum for qe silicon. chapter 13, page 13 - 12 shows time t 167 for wrfull valid as 17 ns maximum. this should be 11 ns maximum for qe silicon. status : the data book to be updated. (11 - 19 - 97) page 2
duplicate of a original document from amcc table of contents 1. whats in the data - books ? 2. what is the s5933 qe ? 3. timings for synchronous rdfifo# and wrfifo# in the 1997 data - book 4. new designs with the s5933 using the fifo is dma mode 1. whats in the data - books ? the spring 1996 data - book was referring to the s5933q timings. we found out by the end of 1996 that some add - on timings required re - simulations for the s5933 qx revisions. thats what we finalized in early 1997. you have received an early version of tho se updated timings for fifo access in spring 1997, valid for the s5933 qa and qb and qc. final timings, also valid for the s5933 qe, now in the 1997 data - book (with two exceptions mentioned further) show some major changes compared to the q timings from sp ring 96. these are real worst case timings valid for the full temperature range, voltage range and taking into consideration the process variations. we do understand those timings may create some trouble. please carefully review the s5933 qe transition des ign note. this will tell you if your application requires any modification. 2. what is the S5933QE ? thanks to costumers feedback, we worked on the improvements we could bring to the part and decided to design the S5933QE. this version brings a 6ns improvem ent on fifo status flag (rdempty and wrfull) availability in synchronous mode compared to the s5933qc. it gives more time for the generation of rdfifo# or wrfifo#. 3. timings for synchronous rdfifo# and wrfifo# in the 1997 data - book please add the following corrections to your 1997 data - book: t165 page 13 - 11 for qc=15ns rdempty valid from bpclk rising edge for qe=12ns t167 page 13 - 12 for qc=17ns wrfull valid from bpclk rising edge for qe=11ns the S5933QE gives more margins for fifo synchronous opera tions. a status signals are valid earlier, the rdfifo# or wrfifo# command can be asserted/de - asserted with sufficient setup time to rising edge of bpclk. 4. new designs with the S5933QE using the fifo is dma mode based on our experience with the s5933 in dma applications using the internal fifos, wed like to give you a few tips on how to successfully implement your add - on interface logic: 1. always use synchronous logic (state machine) to generate strobes and read status (all signals change on a bpclk ris ing edge). 2. use synchronous fifo mode (defined in nvram location 45h, bits 5 - 6=00). 3. only use rdfifo# / wrfifo# signals instead of rd# / wr# to access the fifo. 4. do not use frf or fwe to monitor a dma transfer but only to initiate the transfer. 5. first data of a fifo read is asynchronous: data is valid 12ns max after the falling edge of rdfifo#. all following data is synchronous to bpclk with a setup time of 14ns min and a hold time of 6ns min. please carefully review the fifo timings in figure 1 and figure 2. let suppose the pci bus runs at 33mhz, the bpclk cycle time is then 30ns. fifo write: when the add - on to pci fifo is full, wrfull is asserted 11ns max after the rising edge of bpclk. as wrfifo# requires a 12ns setup, this gives 7ns to de - assert this co mmand before the next bpclk edge. fifo read: when pci to add - on fifo is empty, rdempty is asserted 12ns max after the rising edge of bpclk. as rdfifo# requires an 8ns setup, this gives 10ns to de - assert this command before the next bpclk edge. desig ns with the S5933QE 15 january, 1998 page 3
duplicate of a original document from amcc S5933QE synchronous rdfifo# timing S5933QE synchronous rdfifo# timing functional operation range (v cc =5.0v 5%, 0c to 70c t s 50pf load on outputs) symbol parameter min max units notes t 144 rdfifo# setup to bpclk rising edge 8 26 ns 1 t 145 rdfifo# low time 8 ns t 146 rdfifo# low to dq(31:0) driven 12 ns t 148 rdfifo# high to dq(31:0) float 3 ns t 149 dq(31:0) valid from bpclk rising edge 16 ns 3 t 165 pci to add - on fifo rdempty valid from bpclk rising edge 8 12 ns 2 notes: 1. min and max times are indicated to allow increased valid data time as shown by dashed lines. 2. state change of rdempty shown below is reference only. actual chan ge would indicate no data 3 available. 3. valid applies after first access. first access is async with following as sync accesses. designs with the S5933QE 15 january, 1998 page 4
duplicate of a original document from amcc S5933QE synchronous wrfifo# t iming S5933QE synchronous wrfifo# timing functional operation range (v cc =5.0v 5%, 0c to 70c t s 50pf load on outputs) symbol parameter min max units notes t 150 wrfifo# setup to bpclk rising edge 12 ns t 150e w rfifo# hold time to bpclk rising edge 0 ns t 151 dq(31:0) setup to bpclk rising edge 7 t 151e dq(31:0) hold from bpclk rising edge 0 t 167 add - on to pci fifo wrfull valid from bpclk rising edge 6 11 ns 1 notes: 1. state change of wrfull shown bel ow is reference only. actual change would indicate no data 3 written. designs with the S5933QE 15 january, 1998 page 5
duplicate of a original document from amcc design note s5933 september 6, 1996 errata d8 worka round detail errata d8: bus master burst write operation with an asynchronous fifo interface description : when performing a bus master write to the pci bus, if only one location of the fifo remains full, the s5933 deasasserts frame# on the next clock to indicate the last data phase is in progress. if another value is written from the add - on at the right moment, an internal condition may cause irdy# to remain asserted to sustain the burst, but frame# has already been dasserted. workaround: externally synchronizing wrfifo# or wr# to bpclk moves the rising edge of the write strobe prevents this errata from occurring. the wrfifo# or wr# is to be synced with the rising edge of bpclk. the object of this workaround is to avoid an internal s5933 timing windo w which, when wrfifo# is deasserted in, will cause the errata phenomena to occur. this window is approximately 4ns before the rising edge of pci clk to approximately 4ns after the rising edge of pci clk. the add - on side can detect this window by examining the bpclk. the bpclk signal will always lag the pci clk by the average propagation delay time of an internal s5933 buffer driving bpclk. the average propagation delay time for this buffer is 4ns. therefore, taking this into account and variations in timing windows due to lot variations and temperature, wrfifo# or wr# may be deasserted anytime from 1 ns after the rise of bpclk till its fall. the timing diagram below details this window. d8no te:doc rev 15 january, 1998 page 6
|
